In the past, single first-in-first-out (FIFO) memories were used to buffer data between devices. Data written into a FIFO memory by a first device could be read by a second device at an appropriate time for the second device. Although the implementation of FIFO memories were adequate in some applications, FIFO memories could not be implemented in applications with tighter timing requirements. For example, in some instances the combinational path and the routing delay associated with a path for a read enable signal to the FIFO memory and/or the combinational path on the data output from the FIFO memory were too long. This resulted in requiring the frequency of the system clock to be reduced, which was undesirable.
In order to improve the timing of a system, approaches were taken to break up the combinational paths in a system by inserting flip-flops between combinational logic along the path. The time required to transmit data between the flip-flops along the combinational path may be used to determine the maximum frequency allowed for a system clock. Although adding flip-flops allowed for the frequency of the system clock to be increased, the addition of the flip-flops also changed the synchronization of the intermediate signals between the flip-flops. For each flip-flop added to a combinational path, an additional clock cycle was required to transmit data along the combinational path. This requirement posed a problem for systems requiring data to be supplied within a limited number of clock cycles after it is requested.
Thus, what is needed is a method and apparatus for synchronizing data with a reduced clock cycle response time.